1. Field of the Invention
The present invention relates to semiconductor substrate processing systems. More particularly, the present invention relates to techniques for monitoring the chamber stability and, in response, adjusting a process recipe to optimize substrate processing.
2. Description of the Related Art
Current demands for high density and performance associated with ultra large scale integration require sub-micron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices before the semiconductor wafers are diced into individual circuit chips.
Early detection of chamber fault or process drift is highly desirable, since it can prevent wafer mis-processing, which in turn reduces wafer scrapping, wafer rework and overall device production cost. In the fabrication of active and passive electronic devices on a substrate, a typical substrate has conducting, semiconducting, and dielectric features that form or interconnect the devices on the substrate. Typically, the material is formed on the substrate by, for example, a chemical vapor deposition (CVD), physical vapor deposition, ion implantation, oxidation or nitridation process. Thereafter, some of the substrate materials, which are generally in the form of a layer but may also have other shapes, may be processed, for example by etching, to form features shaped as cavities, channels, holes, vias or trenches.
As technology advances, it requires smaller feature sizes and tighter feature space to improve device performance and to achieve higher device density. It may also be desirable to etch deep features having high aspect ratio to provide faster circuits or otherwise higher signal processing efficiency. The aspect ratio of the feature is the ratio of the feature depth to its opening size. One example of feature patterning is silicon deep trench etch for DRAM trench capacitor fabrication.
In DRAM silicon deep trench capacitor fabrication, the opening size of the trenches may be less than about 0.14 microns and the depth of the trenches may be greater than 7 microns. The aspect ratio of these deep trenches could be higher than 50. It is difficult to etch features having high aspect ratio using conventional substrate processing techniques, especially when the features also have small opening sizes. This high aspect ratio trench etch process is generally sensitive to changes in the process chamber condition and to the sizes of the opening. Chamber condition can greatly affect plasma state and reactant concentration. It is difficult for reactants to penetrate deep into the trench through small openings and difficult for reaction by-products to be transported from inside the trench back out to the substrate surface through the same small openings.
Therefore, there is a need in the art for techniques of monitoring the process conditions of a process chamber to facilitate adapting the process recipe to the process conditions such that the substrate processing is improved.